Responsibilities:

• 
  Implementation of multimillion gate designs in cutting edge process technologies (28nm, 45nm & 65nm).

• Work on all aspects of physical design including synthesis, floor planning, place and route, clock distribution, IP integration, extraction, timing closure, power and signal integrity analysis, physical verification, DFM, and tapeout.

• Clear understanding and command over all aspects of physical design.

• Proficient in timing closure multiple clock domains, IR drop analysis, physical verification, SI/PI, and design closure tasks of IP and/or SoC.

• Work with RTL designers and IP owners to understand the design complexity and plan physical design activities.

• Run equivalence checks across gates-to-gates as design progresses.

Requirements:

• BSEE,MSEE preferred ,5+ years of experience in large VLSI physical design implementation.

• Knowledge of Cadence Virtuoso/VirtuosoXL layout editor, Cadence Soce Encouter P & R tool, Knowledge of Calibre DRC/LVS, Primetime, Star RC ,RF analog or mixed signal layout experience with CMOS, BiCMOS or Bipolar processes .Develop P&R scripts.

• Prior experience in Timing closure, clock/power Distribution and analysis, RC Extraction and correlation, place and route and tapeout issues.

• Successful track record of delivering products to production.